Specialized Singulation Punch Design for Package Chip-out Elimination
Antonio R. Sumagpang Jr, Frederick Ray I. Gomez
Journal of Engineering Research and Reports · pp. 1–7 · Published 20 May 2019
10.9734/jerr/2019/v5i216922Abstract
In the semiconductor manufacturing industry, package chip-out is a common defect frequently encountered in trim and form (T/F) process. For thin shrink small outline package (TSSOP), top defect incurred during assembly manufacturing was the package chip-out located at the top surface of the package. In this scenario, the end-of-line (EOL) process parts per million (PPM) and its non-conformance report (NCR) are high. This paper discussed how the TSSOP20 package (hereinafter referred to as Device A) chip-out was addressed and replicated or simulated through package design simulation.
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Cited by 3
A. Sumagpang, F. Gomez, E. Graycochea · 2020
A. Sumagpang, F. Gomez, R. Rodriguez · Journal of Engineering Research and Reports · 2020
F. Gomez, R. Rodriguez · 2020
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