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Research Article Open access CC BY 4.0

Line Stressing Critical Processes Optimization of Scalable Package Passive Device for Successful Production Ramp-up

Antonio R. Sumagpang Jr, Frederick Ray I. Gomez

Journal of Engineering Research and Reports · pp. 1–13 · Published 14 Dec 2018

10.9734/jerr/2018/v3i116867

Abstract

The technical paper presents a systematic and methodological approach to deal with a new product trend that will be successfully manufactured during assembly production ramp-up.  The project is intended to determine the required process flow and machine platforms for high-density and high-complexity scalable device. Critical processes are shown and top reject contributors are addressed through systematic method by using statistical tools and in-depth engineering analysis. The Scalable Package Passive Device is one of the newest and latest developed device in the plant, which functions as a diode for mobile and computer applications.  The device is considered high density as its 6” single wafer is equivalent to 400,000 units compared to conventional device consisting of only 1,000 units.  Moreover, it is considered as a device with high complexity as state-of-the-art platforms are needed to satisfy its output process.  Furthermore, the device has a very thin die and with the smallest total package dimension.  The process of assembly manufacturing includes a step cutting method of wafers, compression molding, and in-strip testing, which are unlikely to be found on other semiconductor industries. Ultimately, complex errors and top reject contributor of identified critical processes are corrected and the target or required process capability index is effectively achieved.

Scalable package passive device line stressing design of experiments DOE matrix.

References (5)

  1. 1 Handbook of Semiconductor Manufacturing Technology [DOI]
  2. 2 Encapsulation Technologies for Electronic Applications [DOI]
  3. 3 Trends of Power Electronic Packaging and Modeling [DOI]
  4. 4 Trend of semiconductor packaging, high density and low cost [DOI]
  5. 5 Elimination of ESD Events and Optimizing Waterjet Deflash Process for Reduction of Leakage Current Failures on QFN-mr Leadframe Devices [DOI]

Cited by 13

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Antonio R. Sumagpang Jr, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2019

Wafer Tape Selection Analysis for Adhesion Problem Mitigation

Bryan Christian S. Bacquian, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2019

A Study of Wafer Backgrinding Tape Selection for SOI Wafers

Bryan Christian S. Bacquian, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2019

A Study of Vacuum Efficiency for Silicon on Insulator Wafers

Bryan Christian S. Bacquian, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2019

Package and Process Design Augmentation of QFN Leadframe Device

Rennier S. Rodriguez, Maiden Grace R. Maming, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2020

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