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Research Article Open access CC BY 4.0

Die Attach Process Analysis of Enhanced Stand-off Stopper on Tapeless Leadframe

E. Graycochea Jr., F. Gomez, R. Rodriguez, B. Bacquian

Journal of Engineering Research and Reports · pp. 22–26 · Published 13 Mar 2020

10.9734/jerr/2020/v11i117051

Abstract

Improvement on the process and design is often a reliable way to resolve a problem especially in semiconductor industry. This paper presents a leadframe or semiconductor carrier merged with a stand-off design structure that will maintain a consistent bond line thickness (BLT) criteria for quad-flat no-leads (QFN) packages. Through package and process conceptualization, the stand-off design located on the leadframe underneath the silicon die corners would result to a steady and consistent BLT during die attach process. With the improved design, die tilt occurrence in die attach process would be mitigated.

Quad-flat no-leads bond line thickness stand-off design die attach leadframe.

References (6)

  1. 1 Handbook of Semiconductor Manufacturing Technology [DOI]
  2. 2 Printed Circuits Handbook
  3. 3 Die attach capability on ultra thin wafer thickness for power semiconductor [DOI]
  4. 4 Solder Paste in Electronics Packaging: Technology and Applications in Surface Mount, Hybrid Circuits, and Component Assembly
  5. 5 Pick and Place Process Optimization for Thin Semiconductor Packages [DOI]
  6. 6 Semiconductor Manufacturing Handbook

Cited by 4

Die Attach Process Optimization with Enhanced Epoxy Control on Leadframe Package

Rennier S. Rodriguez, Edwin M. Graycochea Jr, Rammil A. Seguido, Frederick Ray I. Gomez · Journal of Engineering Research and Reports · 2020

Pick and Place Process Defect Mitigation on Semiconductor BGA Device

Antonio R. Sumagpang Jr., Frederick Ray I. Gomez, Edwin M. Graycochea Jr. · Journal of Engineering Research and Reports · 2020

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