A Robust 11T SRAM Cell with Improved SNM in 22nm Technology

Abstract

This paper presents a FinFET-based 11-transistor static random-access memory cell designed and evaluated at the 22 nm technology node. The proposed SRAM cell is intended to improve static noise margin while maintaining acceptable power consumption and access time under low-voltage operation. The design separates the read and write paths by introducing an independent single-ended read buffer composed of three NMOS transistors. This separation reduces disturbance at the internal storage nodes during the read operation and improves read stability. Two additional transistors are incorporated in the write circuitry to support data retention and reduce leakage during standby mode. The proposed cell was simulated in HSPICE using a 22 nm BSIM-CMG FinFET model at a supply voltage of 0.8 V. Its performance was compared with conventional 6T, 9T, and ST10T SRAM cells in terms of hold static noise margin, read static noise margin, write static noise margin, static power, read power, write power, and access time. The proposed 11T SRAM cell achieved hold and read static noise margins of 360 mV. Its read static noise margin was 3.91 times, 1.38 times, and 1.89 times higher than those of the 6T, 9T, and ST10T cells, respectively. It also showed a write static noise margin of 375 mV, static power of 490 pW, read power of 0.139 µW, write power of 1.43 µW, and write access time of 23.5 ps. The results indicate improved read and hold stability with moderate power and timing characteristics.