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Research Article Open access CC BY 4.0

Validation of New Substrate Design for the Improvement of Strip Warpage on LGA Packages

Jerome Dinglasan, Mariane Mendoza

Journal of Engineering Research and Reports · pp. 50–56 · Published 29 Aug 2022

10.9734/jerr/2022/v23i317600

Abstract

Land grid array or LGA package of semiconductor has been commonly used on our modern technology, from home gadgets up to industrial uses. Improvements to correct product defects and process issues are introduced to have quality products for customer satisfaction. Substrate warpage have been affecting production performance on semiconductor manufacturing. The unacceptable response results to loss of productivity losses and yield detraction. Different process improvements have been experimented to contain the problem, but results are not maintained and found to be not robust. This is where design innovation plays the part. Solder mask opening on the base material of the substrate is considered to have a favorable response after subjecting it to different environment conditions. From fast indexing and machine movement up to high thermal application on oven curing, having a robust solder mask design makes the unit acceptable and with quality. Product design as mentioned takes on another level to address the phenomenon of substrate warpage. This manuscript will be discussing how the solder mask of the substrate is optimized to achieved minimal or zero substrate warpage by performing different experiments on process and the product itself. Statistical analysis has been the basis for the implementation of the newly validated substrate design.

Front-of-line land grid array MEMS solder mask opening substrate design warpage

References (6)

  1. 1 Simulation methodology development of warpage estimation for epoxy molding compound under considerations of stress relaxation characteristics and curing conditions applied in semiconductor packaging [DOI]
  2. 2 Substrate Trace Modeling for Package Warpage Simulation [DOI]
  3. 3 Block-Based Finite Element Modeling, Simulation, and Optimization of the Warpage of Embedded Trace Substrate [DOI]
  4. 4 Understanding Jig Alignment Error Occurrences for Substrate 1-Map Strips [DOI]
  5. 5 Effects of Substrate Structure on the Warpage of Flip Chip IC Packages [DOI]
  6. 6 A comprehensive packaging solution for next generation IC substrates

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