Manufacturing and Electrical Characterization of MOS Devices of Ultrathin Silicon Dioxide Layer

Abstract

Metal-Oxide-Semiconductor–MOS devices presented here with thermally grown oxide layer of 3.04-5.92 nm thick were fabricated using p-type Si substrate. Capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics in frequency range of 10 kHz-100 kHz between 22 and 100 °C were measured in darkness. Current-voltage (I-V) was measured at Troom in darkness. C-V and G/ω-V at various frequencies revealed the energy distribution of MOS interface states. Current transport mechanisms in the device were studied and the I-V was generally characterised by Fowler-Nordheim and direct tunnel mechanisms of current carriers transport. Interface state density, flat-band voltages and frequency dispersion were extracted from C-V measurements. The frequency dispersion indicates the presence of either interface traps or laterally inhomogeneous distribution of defect centres near Si/SiO2 interface. The concentration of charged defects and their location at Si/SiO2 interface were calculated from frequency characterization. Small densities of interface traps < 2×1011 eV-1 cm-2 show that SiO2-Si interface has reliable qualities and its oxide may find applications in CMOS as dielectric gates. C-V of sample of dox = 4.14 nm was used to calculate at (22, 30, 50, 75, 100°C) the capacitance in accumulation mode, interface charge density, flat band voltage, threshold voltage and density of interface traps (in minimum position), Dit,= 0.3×1011-1×1011 cm-2. G/ω-V characteristics at Troom for sample of dox = 4.14 nm at 10 kHz, 50 kHz and 100 kHz were obtained. C-V of all 4 samples at Troom was also used to calculate the mentioned oxide properties. Two samples of dox = 3.04 nm and 4.14 nm were studied using X-ray photoelectron spectroscopy technique and evaluation of Si 2p peak was obtained for dox = 3.04 nm. Exact SiO2 thickness for all samples was measured by an ellipsometer.