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Research Article Open access CC BY 4.0

Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers

Daniel Etiemble, Ramzi A. Jaber

Asian Journal of Research in Computer Science · pp. 103–118 · Published 15 Jul 2023

10.9734/ajrcos/2023/v16i3349

Abstract

The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.

CNTFET ternary counters wallace trees combinational multipliers

Cited by 5

Proposed a Ternary Multiplexer using CNTFET

Ramzi A. Jaber, El Moucary Chady, Abdallah Kassem · 2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 2025

Proposed Two Ternary Decoders Using CNTFET

Ramzi A. Jaber, Hiba S. Bazzi, Abdallah Kassem · 2024 International Conference on Microelectronics (ICM) · 2024

Proposed a Ternary Adder Using CNTFET

Ramzi A. Jaber · 2025 37th International Conference on Microelectronics (ICM) · 2025

Proposed a Ternary Inverter and a Ternary Decoder using CNTFET

Ramzi A. Jaber, El Moucary Chady, Abdallah Kassem · 2025 Sixth International Conference on Advances in Computational Tools for Engineering Applications (ACTEA) · 2025

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