Wafer Saw Process Optimization for Die Chipping Mitigation on Extremely Small Leadframe Package

Abstract

The paper focused in addressing the silicon die chippings defect at the wafer sawing process of an extremely small semiconductor package. In-depth potential risk analysis and Pareto diagram were done to identify the top reject contributors and eventually resolve the issue. A comprehensive design of experiment (DOE) was done and validation of the solution was employed to formulate the effective corrective actions. Results revealed that die chippings were addressed by optimizing the wafer sawing process through enabling the dressing, pre-cut and step-cutting modes. Ultimately, an improvement of 95% for die chippings reduction was achieved.