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Research Article Open access CC BY 4.0

Enhanced Wirebonding Technique on QFN Device with Critical Die Reference

Jonathan C. Pulido, Frederick Ray I. Gomez

Journal of Engineering Research and Reports · pp. 57–61 · Published 11 Mar 2021

10.9734/jerr/2021/v20i317283

Abstract

Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimization particularly on wirebond looping was done to ensure that the silicon die’s L-fiducial is visible and not obstructed by the wires, which is the operator point or die reference of the unit during wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the pattern recognition alignment error and misplaced ball issues during the lot process.  For future works, the configuration and technique could be applied on packages with the similar situation.

Die reference J-wire looping profile pattern recognition wirebonding process.

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A Systematic Approach to Reduce Wirebond defects caused by Tight Wire Loop Profile on Ball Grid Array Packages

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