Mechanical modeling of integrated circuit (IC) dies is commonly performed using the mechanical properties of the bulk silicon material. However, modeling results such as die deflection and the actual results were observed to have significant difference. This paper discusses the i...
Open access
Research Article10.9734/jerr/2021/v20i1017389
This paper discusses the modeling approach used in improving the solder joint reliability prediction for Quad Flat No Lead (QFN) packages. A new power equation fatigue prediction model was developed based on the accumulated creep strain energy density from FEA (finite element ana...
Open access
Research Article10.9734/jerr/2021/v20i717344
A semiconductor package has a silicon die on which an integrated circuit (IC) is fabricated. The die is singulated from a single wafer using processes like mechanical sawing or laser grooving. These processes have impact on the final condition of the silicon die after wafer singu...
Open access
Research Article10.9734/jerr/2021/v20i617328
Die fracture strength measurement is important to assess the robustness of a specific silicon die such that it is strong enough to resist die crack. There are several methods used to measure the strength of silicon die and 3-point bend test is the most common. However, the impact...
Open access
Research Article10.9734/jerr/2021/v20i617323
Strip warpage is a common problem in molded leadframe packages. When warpage becomes excessive, the strip could not be processed as it would result in the strip being stuck or damaged during loading to the handling machine loader. This study focuses on the impact of mold cap thic...
Open access
Research Article10.9734/jerr/2021/v20i517312
Thinner semiconductor package is becoming popular especially in consumer electronics applications. As package becomes thinner, it is more vulnerable to package crack when subjected to external load. It is important to ensure that the package is strong enough to resist package cra...
Open access
Research Article10.9734/jerr/2021/v20i517311
Die crack is a common problem in the semiconductor industry and being able to predict the breaking force at a given loading condition could help prevent such crack problem. This paper presents the use of mechanical simulation in predicting the force at which the silicon die break...
Open access
Research Article10.9734/jerr/2021/v20i517307
Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure...
Open access
Research Article10.9734/jerr/2021/v20i417295
Die crack is one of the problems in stacked die semiconductor packages. As silicon dies become thinner in such packages due to miniaturization requirement, the tendency to have die crack increases. This study presents the investigation done on a die crack issue in a stacked die p...
Open access
Research Article10.9734/jerr/2021/v20i317285
In the leadframe package assembly process, silicon die is attached to the leadframe using a die attach adhesive material and the bonded strip is then cured. However, excessive strip warpage after the die attach cure process is a challenging problem that also affects the succeedin...
Open access
Research Article10.9734/jerr/2021/v20i317281
This paper aims to present a thermo-mechanical modeling approach to predict the solder joint reliability of a leadframe-based package under powered thermal cycling (PTC) test from -40oC to 105oC. The study involves modeling the PTC condition as a standard thermal cycling with a m...
Open access
Research Article10.9734/jerr/2021/v20i317279
This paper presents the simulation approach used to understand package crack signatures of a leadframe package under different mechanical loading scenarios. Package crack is one of the common problems with semiconductor packages. A better understanding of the different crack sign...
Open access
Research Article10.9734/jerr/2021/v20i317274
Interface adhesion tests are conducted to obtain a quantitative value of the adhesion strength or interface fracture toughness to forecast initiation and propagation of interface delamination failures in semiconductor packages. One of the common methods of fracture mechanics inte...
Open access
Research Article10.9734/jerr/2021/v20i217282
Package delamination is one of the problems in semiconductor packaging. Understanding the delamination mechanism in a specific situation is very important to identify the root cause and implement robust solution. In this study, package deformation modeling was done to analyze the...
Open access
Research Article10.9734/jerr/2021/v20i217278
Pick-and-place (PnP) rubber tip is used for the die attach process in semiconductor packaging. During the die attach process involving a very thin integrated circuit (IC) die, voids in the die attach film (DAF) adhesive were observed. This paper presents the modeling study conduc...
Open access
Research Article10.9734/jerr/2021/v20i217269
Very thin semiconductor package is very prone to package crack. This paper discusses the stress modeling study conducted to understand the package crack problem in a specific smart card package. Finite element analysis (FEA) was used to analyze the maximum package stress level an...
Open access
Research Article10.9734/jerr/2021/v20i217271
This paper discusses the characterization of an integrated circuit (IC) silicon die fracture strength to have a realistic die crack assessment. The evaluation was conducted using a 3-point bend test setup to measure the die strength of actual IC dies. Both the active side and the...
Open access
Research Article10.9734/jerr/2021/v20i217267
Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and...
Open access
Research Article10.9734/jerr/2019/v7i216966
This paper presents the submodeling approach in thermo-mechanical simulation of the die passivation crack encountered in a power leadframe package subjected to temperature cycling condition. Without using modeling and simulation in resolving semiconductor package development iss...
Open access
Research Article10.9734/jerr/2019/v7i216964
Semiconductor packages using solder balls as interconnect to the printed circuit board (PCB) are very popular especially in mobile products like smart phones. Recent requirement to make the package much thinner is very challenging. The solder ball collapse height after the solder...
Open access
Research Article10.9734/jerr/2019/v7i116962